By Jose M. de la Rosa, Rocio del Rio(auth.)
A entire review of Sigma-Delta Analog-to-Digital Converters (ADCs) and a pragmatic advisor to their layout in nano-scale CMOS for optimum performance.
This e-book provides a scientific and complete compilation of sigma-delta converter working rules, the hot advances in architectures and circuits, layout methodologies and sensible issues ? going from system-level necessities to silicon integration, packaging and meaurements, with emphasis on nanometer CMOS implementation. The publication emphasizes functional layout matters – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence layout FrameWork II. in addition to being a accomplished connection with the idea, the e-book is additionally designated in that it provides specified value on sensible matters, giving a close description of the various steps that represent the total layout move of sigma-delta ADCs.
The publication starts with an introductory survey of sigma-delta modulators, their basics architectures and synthesis equipment coated in bankruptcy 1. In bankruptcy 2, the impression of major circuit mistakes mechanisms is analysed, offering the mandatory knowing of the most useful matters affecting the functionality of sigma-delta modulators. the information derived from the 1st chapters is gifted within the e-book as a necessary a part of the systematic top-down/bottom-up synthesis technique of sigma-delta modulators defined in bankruptcy three, the place a time-domain behavioural simulator named SIMSIDES is defined and utilized to the high-level layout and verification of sigma-delta ADCs. bankruptcy four strikes farther down from system-level to the circuit and actual point, delivering a few layout thoughts and functional recipes to accomplish the layout circulate of sigma-delta modulators. To finish the publication, bankruptcy five supplies an outline of the cutting-edge sigma-delta ADCs, that are exhaustively analysed with a purpose to extract functional layout guidance and to spot the incoming tendencies, layout demanding situations in addition to sensible options proposed through state of the art designs.
• deals an entire survey of sigma-delta modulator architectures from basics to state-of-the paintings topologies, contemplating either switched-capacitor and continuous-time circuit implementations
• provides a scientific research and useful layout advisor of sigma-delta modulators, from a top-down/bottom-up viewpoint, together with mathematical types and analytical tactics, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence layout FrameWork II, chip prototyping, and experimental characterization.
• Systematic compilation of state-of-the-art sigma-delta modulators
• whole description of SIMSIDES, a time-domain behavioural simulator applied in MATLAB/SIMULINK
• lots of examples, case experiences, and simulation try benches, masking the various levels of the layout move of sigma-delta modulators
• a few digital assets, together with SIMSIDES, the statistical info utilized in the cutting-edge survey, in addition to many layout examples and try benches are hosted on a better half website
Essential analyzing for Researchers and electronics engineering practitioners attracted to the layout of high-performance facts converters built-in in nanometer CMOS applied sciences mixed-signal designers.
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Additional resources for CMOS Sigma-Delta Converters: Practical Design Guide
5-bit) quantizers  are also often employed, as they yield a 3-dB reduction of the quantization error power compared to 1-bit quantization. Although trilevel coding is not inherently linear, it is often used in fully-differential SC Ms, because highly linear trilevel DACs can be easily implemented using just one extra switch . 7 Band-Pass Modulators The operation principle of low-pass modulators (LPMs)—in which the quantization noise is high-pass shaped for its suppression around DC—can be extended to the more general case of stop-band filtering of the quantization noise for its suppression around a nonzero frequency in a so-called band-pass modulator (BPM) [72, 73].
14b shows an alternative representation of the second-order M according to the coefficients notation in [12, 19], which allows to allocate different weights in the forward and feedback paths of each integrator, using coefficients gi and g i , respectively. 27) Both nomenclatures for the integrator scaling coefficients of modulators will be used throughout this book. The notation in [8, 9] is closer to the modulator architectural level, whereas the notation in [12, 19] is closer to the actual circuit-level implementation, in which integrators with more than one SC input branch are usually employed.
Consequently, the linearity of a multibit M will be no better than that of the multibit embedded DAC and the latter must be designed to achieve the linearity targeted for the whole ADC, what may be challenging under the influence of component mismatching. 25 conceptually illustrates the parallel architecture that is typically used for the multibit quantizer in Ms, in which the resolution is usually low (B ≤ 5). The B-bit ADC consists of a bank of 2B − 1 comparators that digitizes the loop filter output into thermometer code, which will be subsequently coded into binary.