By Reis R., Jess J.A.G.
Layout of method on a Chip is the 1st of 2 volumes addressing the layout demanding situations linked to new generations of the semiconductor know-how. a few of the chapters are the compilations of tutorials offered at workshops in Brazil within the contemporary years by means of in demand authors from around the globe. particularly the 1st publication offers with elements and circuits. gadget versions need to fulfill the stipulations to be computationally low-cost as well as be actual and to scale over a number of generations of know-how. moreover the publication addresses problems with the parasitic habit of deep sub-micron elements, equivalent to parameter diversifications and sub-threshold results. moreover a number of authors take care of goods like combined sign parts and thoughts. We finally end up with an exposition of the know-how difficulties to be solved if our neighborhood desires to continue the velocity of the "International know-how Roadmap for Semiconductors" (ITRS).
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Extra info for Design of System on a Chip: Devices & Components
Forward output modeling comparison. 2 BTJ Modeling with VBIC 39 Figure 7. Output conductance modeling, from data of figure 6 7. ELECTROTHERMAL EXAMPLES The coupled electrothermal (self heating) modeling capability is a major feature of VBIC. Self heating is significant for GaAs HBTs, because the thermal conductivity of GaAs is relatively low. In contrast to silicon BJTs, GaAs HBTs have a negative temperature coefficient for ` = Ic ⁄ Ib. This means that for a fixed base current drive the collector current Ic decreases as temperature increases.
36 Chapter 2 Existing methods can be used to obtain initial values for the resistances. This can be difficult, and it is desirable to include both DC and AC data. Many of the simple procedures that have been proposed for BJT resistance calculation are based on oversimplifications of the model, and do not give realistic values. Optimization is used to refine the initial values, again preferably using DC and AC data. The quasisaturation parameters are likewise obtained by optimization to output curves that show significant quasi-saturation effects.
Turgeon, L. J. and Mathews, J. R. (1980) A bipolar transistor model of quasisaturation for use in computer-aided design (CAD). Proc. IEEE IEDM, 394-7. Vogelsong, R. S. and Brzezinski, C. (1989) Simulation of thermal effects in electrical systems. Proc. IEEE APEC, 353-6. Weil, P. B. and McNamee, L. P. (1978) Simulation of excess phase in bipolar transistors. IEEE Trans. , 2, 114-6. 2 BTJ Modeling with VBIC 12. D. Sc. E. , Australia, in 1978. Since 1995 he has been the Manager of the Statistical Modeling and Characterization Laboratory at Motorola, Tempe AZ.