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14 The developers based vital components such as local clock generators and asynchronous port controllers on silicon-proven earlier implementations. They also found that a standard hierarchical back-end design flow is well-suited to GALS systems. In this approach, the asynchronous wrapper occupies an additional level of hierarchy around the locally synchronous island. The project also tackled the challenge of providing a test solution. 89%. 17 Faust, an open platform for fourth-generation multicarrier code division multiple-access (MC-CDMA) telecommunications applications, was designed to validate the principles and feasibility of an innovative GALS NoC architecture.

11th IEEE Int’l GALS Design,’’ IEE Proc. Computers & Digital Symp. Asynchronous Circuits and Systems (ASYNC 05), Techniques, vol. 153, no. 5, Sept. 2006, pp. 362-372. IEEE CS Press, 2005, pp. 44-53. 7. R. Mullins and S. Moore, ‘‘Demystifying Data-Driven and Pausible Clocking Schemes,’’ Proc. 13th IEEE Int’l Symp. Asynchronous Circuits and Systems (ASYNC 07), IEEE CS Press, 2007, pp. 175-185. 8. T. Chelcea and S. Nowick, ‘‘Low-Latency Asynchronous 19. G. DeMicheli and L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann, 2006.

12,18 The ANOC is implemented in quasi-delay-insensitive asynchronous logic. 10 Compared with a more optimized FIFO solution,8 the Faust design adapts classical bisynchronous FIFO buffers with gray code, which are compatible with standard CAD tools. The FIFO design lets users robustly interface the NoC protocol with high throughput (one transfer per clock cycle) and small latency overhead (two clock cycles). IEEE Design & Test of Computers Previous Page | Contents | Zoom in | Zoom out | Front Cover | Search Issue | Next Page A BEMaGS F Previous Page | Contents | Zoom in | Zoom out | Front Cover | Search Issue | Next Page For off-chip NoC communication, a dual synchronous/ asynchronous-mode NoC port allows connection of different NoC-based subsystems.

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