Download Noise-Shaping All-Digital Phase-Locked Loops: Modeling, by Francesco Brandonisio, Michael Peter Kennedy PDF

By Francesco Brandonisio, Michael Peter Kennedy

This ebook provides a unique method of the research and layout of all-digital phase-locked loops (ADPLLs), know-how ordinary in instant communique units. The authors offer an outline of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. lifelike examples illustrate how you can research and simulate section noise within the presence of sigma-delta modulation and time-to-digital conversion. Readers will achieve a deep knowing of ADPLLs and the crucial function performed by way of noise-shaping. various ADPLL and TDC architectures are offered in unified demeanour. Analytical and simulation instruments are mentioned intimately. Matlab code is incorporated that may be reused to layout, simulate and examine the ADPLL architectures which are offered within the book.

• Discusses intimately a variety of all-digital phase-locked loops architectures;
• offers a unified framework within which to version time-to-digital converters for ADPLLs;
• Explains a method to foretell and simulate part noise in oscillators and ADPLLs;
• Describes a good method of version ADPLLS;
• comprises Matlab code to breed the examples within the book.

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Additional info for Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design

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S. Evani, N. P. Nayak, I. Prathapan, F. Zhang, B. Haroun, “Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops”, IEEE Trans. Circuits Sys. I: Regular Papers, vol. 60, no. 3, pp. 517–528, Apr. 2013. 5. -M. Hsu, M. Z. Straayer, M. H. 6-GHz Digital ≤Ω Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776– 2786, Dec. 2008. 6. -C. -I. Liu, “A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm,” IEEE Trans.

2776– 2786, Dec. 2008. 6. -C. -I. Liu, “A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm,” IEEE Trans. Circuits Sys. II: Express Briefs, vol. 58, no. 6, pp. 321–325, Jun. 2011. 7. N. Da Dalt, “Theory and Implementation of Digital Bang-Bang Frequency Synthesizers for High Speed Serial Data Communications,” PhD Thesis, RWTH Aachen University, Feb. 2007. 8. R. B. Staszewski, “State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS,” IEEE Trans.

321–325, Jun. 2011. 7. N. Da Dalt, “Theory and Implementation of Digital Bang-Bang Frequency Synthesizers for High Speed Serial Data Communications,” PhD Thesis, RWTH Aachen University, Feb. 2007. 8. R. B. Staszewski, “State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS,” IEEE Trans. Circuits Sys. I: Regular Papers, vol. 58, no. 7, pp. 1497–1510, Jul. 2011. 9. R. B. Staszewski, P. T. , 2006. 10. S. Mendel, C. Vogel, N. Da Dalt, “A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming,” IEEE Trans.

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